1. Field of the Invention
The present invention relates to a reconfigurable circuit.
2. Description of the Related Art
A reconfigurable circuit can be reconfigured by dynamically switching a plurality of function circuits. An address generation function circuit realizes simple one-dimensional consecutive address generation and simple two-dimensional address generation. As the circuit configuration, the function is provided by including one (one dimension) or a plurality of (two dimension or more) simple incremental circuits. As operation procedure, it runs in response to trigger, and performs relatively simple operation only.
In a patent document 1 below, a data transfer address generation device using an ALU is described. A request address data which is output from a bus master to a slave unit is stored in a request address register. Signal which specifies ordering from the bus master is decoded in a system bus interface section, and any address table is selected by a multiplexer. A count value of a binary counter which is incremented in response to a count clock is translated into address table data by the selected address table and supplied to the ALU via the multiplexer. The address table data and the request address data are added at the ALU, as a result, when a sign bit indicates an invalid address, the binary counter is further incremented. The address data from the ALU is masked by a mask circuit to generate transfer address data.
In a patent document 2 below, a digital signal processor to perform address generation is described. In the digital signal processor, which comprises a plurality of data input buses which transmit input data signal, a data memory which receives respective input data signal from the data input buses and stores the input data signal therein, an arithmetic section which receives input data signal being output from the data memory and performs arithmetic processing, and an address generation section which controls the operation of the arithmetic section and the data memory, a data input/output word length in the arithmetic section and a word length of the address operation in the address generation section are set to be the same, and an operation data calculated in the arithmetic section is set as an address of the address generation section.
[Patent document 1] Japanese Patent Application Laid-open No. Hei 7-319762
[Patent document 2] Japanese Patent Application Laid-open No. Hei 7-168713
In a reconfigurable circuit, only a simple incremental circuit for address generation is provided, which makes it difficult to perform sophisticated address generation.